Pixel array substrate and liquid crystal display panel

ABSTRACT

A pixel array substrate with new pixel design and a liquid crystal display panel with the pixel array substrate are provided. The pixel array substrate includes a plurality of data lines, a plurality of scan lines and a plurality of pixels. Each of the pixels comprises a first electrode, a first connecting line, a second electrode and a second connecting line. The first electrode is electrically connected with corresponding data line and scan line through the first connecting line, and having a slit. The second pixel is electrically connected with corresponding data line and scan line through the second connecting line. At least a part of the second connecting line is exposed by the slit of the first electrode.

RELATED APPLICATIONS

The present application is a continuation application of U.S.application Ser. No. 14/041,071, filed Sep. 30, 2013, which claimspriority to Taiwan Application Serial Number 102102336, filed Jan. 22,2013, which are herein incorporated by reference in their entireties.

BACKGROUND

Technical Field

The present disclosure relates to a substrate, and more particularly, toa pixel array substrate of a display panel

Description of Related Art

Liquid crystal display (LCD) panels have become the mainstream displayproducts because of advantages such as low radiation, low powerconsumption and compact size. A variety of techniques in the LCD panelsare developed corresponding to different needs. Among which, VerticalAlignment (VA) of the wide viewing angle display technology has widerviewing angle than that of Twisted Nematic (TN), fast responding, andhigh contrast ratio, thus has been widely applied in a LCD panel.

However, the VA LCD panel is known for its color washout issue. To solvethe issue, the pixel area of the pixel array substrate of current VA LCDpanels is divided into two parts. As illustrated in FIG. 1 and FIG. 2,FIG. 1 is a top-view of the conventional pixel, and FIG. 2 is theequivalent circuit diagram of the pixel illustrated in FIG. 1. Referringto FIG. 1 and FIG. 2, pixel 100 includes a first pixel electrode 102, asecond pixel electrode 104, a first connecting line 106, and a secondconnecting line 108. The first electrode 102 is electrically connectedto its corresponding data line DL1 and scan line SL1 through the firstconnecting line 106 and the a switch T1; The second pixel electrode 104is also electrically connected to its corresponding data line DL1 andscan line SL1 through the second connecting line 108 and a switch T2. Inaddition, pixel 100 also includes a switch T3, storage capacitorsC_(ST1), C_(ST2), common electrode V_(COM), liquid crystal capacitorsC_(LC1), C_(LC2), and charge-sharing capacitor Cs (C_(CSA) and C_(CSB)).Switches T1, T2, and T3 are thin-film transistors (TFT), for example.Liquid crystal capacitors C_(LC1), C_(LC2) respectively represent thecapacitances which are generated between pixel electrode (the firstpixel electrode 102 and the second pixel electrode 104) and theelectrode(s) applied with V_(COM) voltage on the opposite substrate ofthe LCD panel (not illustrated in FIG. 1 and FIG. 2). C_(ST1) andC_(ST2) respectively represent the capacitances which are generatedbetween common electrode applied with V_(COM) voltage and each pixelelectrode (the first pixel electrode 102 and the second pixel electrode104) of the pixel array substrate of the LCD panel. Charge-sharingcapacitor Cs is an extension from the switch T3, charge-sharingcapacitor Cs forms capacitors with other conductive layers, for example,C_(CSA) is the capacitor formed between the first pixel electrode 102and Cs, and C_(CSB) is the capacitor formed between the common electrodeV_(COM) and Cs.

As to the main display area which corresponds to the first pixelelectrode 102, the switch T1 is electrically connected between data lineDL1 and the first pixel electrode 102. The switch T1 is alsoelectrically connected to scan line SL1, and a signal passing throughscan line SL1 controls the switch T1 to turn on/off. The storagecapacitor C_(ST1) is electrically connected between the first pixelelectrode 102 and the common electrode V_(COM). When the switch T1 turnson, a data signal of data line DL1 is transmitted through the switch T1to the first electrode 102, so that the storage capacitor C_(ST1) ischarged to have corresponding voltage.

As to the secondary display area which is corresponding to the secondpixel electrode 104, the switch T2 is electrically connected betweendata line DL1 and the second pixel electrode 104. The switch T2 is alsoelectrically connected to scan line SL1, a signal passing through scanline SL1 controls the switch T2 to turn on/off. The storage capacitorC_(ST2) is electrically connected between the second pixel electrode 104and the common electrode V_(COM). When the switch T2 turns on, a datasignal of data line DL1 is transmitted through the switch T2 to thesecond electrode 104, so that the storage capacitor C_(ST2) is chargedto have corresponding voltage. To solve the issue of color washout ofthe LCD panel, charge sharing is performed. After the first pixelelectrode 102 and the second pixel electrode 104 are charged by thesignal from scan line SL1, in next time sequence, the switch T3 turns onby the signal inputted from scan line T3, so as a part of the voltage ofthe second pixel electrode 104 is shared to the capacitor C_(CSB) andthe other part of the voltage of the second pixel electrode 104 isshared to the capacitor C_(CSA) through the switch T3. It results incharge sharing between the first pixel electrode 102 and the secondpixel electrode 104 by the charge-sharing capacitor Cs, the voltage ofthe first pixel electrode 102 increases and that of the second pixelelectrode 104 decreases. Therefore, the voltages of the first pixelelectrode 102 and the second pixel electrode 104 are different. Itcauses the tilting angle of liquid crystals corresponding to the firstpixel electrode 102 and the second pixel electrode 104 are differentwithin the same pixel 100, so as the brightness within the same pixel100 can be optimized since the transmittance within the same pixel 100can be different, thus the issue of color washout can be solved.

However, continually referring FIG. 1 and FIG. 2, as illustrated in dotlines area of FIG. 1, in the path of the second connecting line 108connecting to the second pixel electrode 104, part of the path isunderpass the first pixel electrode 102. This overlapping structure ofthe second connecting line 108 and the first pixel electrode 102 invertical direction will generate an extra coupling capacitance Cx asillustrated in dot lines area of FIG. 2. When the coupling capacitanceCx is generated between the first pixel electrode 102 and the secondpixel electrode 104, charge sharing will be weaken. Thus the effects ofthe voltage increase of the first pixel electrode 102 and the voltagedecrease of the second pixel electrode 104 are diminished. Therefore, toincrease the voltage difference between the first pixel electrode 102and the second pixel electrode 104 becomes difficult. In order tomaintain the voltage difference between the first pixel electrode 102and the second pixel electrode 104 to solve the color washout issue,further increase the capacitance of the charge-sharing capacitor Cs torelease more electric charge from the second pixel electrode 104 andlower the voltage of the second pixel electrode 104 is generallyperformed. However, the efficiency of the LCD panel is decreased tomaintain the voltage difference between the first pixel electrode 102and the second pixel electrode 104 in this way.

SUMMARY

The present disclosure relates to an array substrate of a display panel,which has a whole new design of pixel layout. The coupling capacitanceCx of the pixel array substrate in the present disclosure is much lessthan that of prior arts, the difficulty of increasing the voltagedifference between the first pixel electrode and the second pixelelectrode is obviously improved. Therefore, LC efficiency and the openratio of the pixel array substrate of the present disclosure areimproved under the premise of solving the issue of color washout.

The present disclosure, in one aspect, relates to a pixel arraysubstrate includes a plurality of data lines, a plurality of scan lines,and a plurality of pixels. The plurality of scan lines is crossed to theplurality of data lines to define a plurality of pixel areas. Theplurality of pixels is respectively disposed in the plurality of pixelareas, each pixel includes a first pixel electrode, a first connectingline, a second pixel electrode, and a second connecting line. The firstpixel electrode is electrically connected to corresponding one of thedata lines and one of the scan lines, and the first pixel electrode hasa first slit. The first pixel electrode is electrically connected tocorresponding data line through the first connecting line. The secondpixel electrode is electrically connected to corresponding data line andscan line. The second pixel electrode is electrically connected tocorresponding data line through the second connecting line, wherein atleast a part of the second connecting line is exposed by the first slitof the first pixel electrode.

In one embodiment of the present disclosure, the first slit is an openslit.

In another embodiment of the present disclosure, the first slit is aclosed slit.

In one embodiment of the present disclosure, the first slit issubstantially parallel to the plurality of data lines.

In one embodiment of the present disclosure, the first connecting lineand the second connecting line are electrically connected to the samedata line.

In another embodiment of the present disclosure, the first connectingline and the second connecting line are electrically connected todifferent data lines.

In one embodiment of the present disclosure, the first pixel electrodeincludes a first sub-pixel electrode and a second sub-pixel electrode,and the first slit is substantially positioned between the firstsub-pixel electrode and the second sub-pixel electrode.

In one embodiment of the present disclosure, the first sub-pixelelectrode and the second sub-pixel electrode are mirror symmetrystructures with respect to the first slit.

In one embodiment of the present disclosure, the first sub-pixelelectrode includes a first main electrode, a second main electrode, aplurality of first branch electrodes, a plurality of second branchelectrodes, a plurality of third branch electrodes, and a plurality offourth branch electrodes. The first main electrode and the second mainelectrode are electrically connected and are substantially orthogonallyarranged to define a first area, a second area, a third area and afourth area. The plurality of first branch electrodes is disposed in thefirst area. The plurality of second branch electrodes is disposed in thesecond area. The plurality of third branch electrodes is disposed in thethird area. The plurality of fourth branch electrodes is disposed in thefourth area. The plurality of first branch electrodes, the plurality ofsecond branch electrodes, the plurality of third branch electrodes andthe plurality of fourth branch electrodes are electrically connectedwith one of the first main electrode and the second main electrode, thefirst branch electrodes are arranged parallel to each other, the secondbranch electrodes are arranged parallel to each other, the third branchelectrodes are arranged parallel to each other and the fourth branchelectrodes are arranged parallel to each other, and the plurality offirst branch electrodes, the plurality of second branch electrodes, theplurality of third branch electrodes and the plurality of fourth branchelectrodes respectively extend to different directions from the firstmain electrode or the second main electrode, the first sub-pixelelectrode and the second sub-pixel electrode are mirror symmetrystructures with respect to the first slit.

In one embodiment of the present disclosure, the first main electrode issubstantially parallel to the first slit, and the distance between thefirst main electrode and the first slit is greater than that of thefirst main electrode and the data line which is adjacent to the firstmain electrode.

In one embodiment of the present disclosure, each pixel further includesa third pixel electrode and a third connecting line. The third pixelelectrode is electrically connected to corresponding data line and scanline, and the third pixel electrode has a second slit. The third pixelelectrode is electrically connected to corresponding data line throughthe third connecting line, wherein at least a part of the secondconnecting line is exposed by the first slit of the first pixelelectrode and the second slit of the third pixel electrode.

In one embodiment of the present disclosure, the third connecting lineis disposed on an edge of the first sub-pixel electrode or the secondsub-pixel electrode.

In one embodiment of the present disclosure, the third pixel electrodeincludes a third sub-pixel electrode and a fourth sub-pixel electrode,the second slit is substantially positioned between the third sub-pixelelectrode and the fourth sub-pixel electrode, and the second slit issubstantially positioned in the extending line of the first slit.

In one embodiment of the present disclosure, the first slit and thesecond slit are substantially parallel to the plurality of data lines,the first sub-pixel electrode and the second sub-pixel electrode aremirror symmetry structures with respect to the first slit, the thirdsub-pixel electrode and the fourth sub-pixel electrode are mirrorsymmetry structures with respect to the second slit.

In one embodiment of the present disclosure, wherein the third sub-pixelelectrode and the fourth sub-pixel electrode respectively include afirst main electrode, a second main electrode, a plurality of firstbranch electrodes, a plurality of second branch electrodes, a pluralityof third branch electrodes, and a plurality of fourth branch electrodes.The first main electrode and the second main electrode are electricallyconnected and are substantially orthogonally arranged to define a firstarea, a second area, a third area and a fourth area. The plurality offirst branch electrodes is disposed in the first area. The plurality ofsecond branch electrodes is disposed in the second area. The pluralityof third branch electrodes is disposed in the third area. The pluralityof fourth branch electrodes is disposed in the fourth area, wherein theplurality of first branch electrodes, the plurality of second branchelectrodes, the plurality of third branch electrodes and the pluralityof fourth branch electrodes are electrically connected with one of thefirst main electrode and the second main electrode, the first branchelectrodes are arranged parallel to each other, the second branchelectrodes are arranged parallel to each other, the third branchelectrodes are arranged parallel to each other and the fourth branchelectrodes are arranged parallel to each other, and the plurality offirst branch electrodes, the plurality of second branch electrodes, theplurality of third branch electrodes and the plurality of fourth branchelectrodes respectively extend to different directions from the firstmain electrode or the second main electrode, the first sub-pixelelectrode and the second sub-pixel electrode are mirror symmetrystructures with respect to the first slit, the third sub-pixel electrodeand the fourth sub-pixel electrode are mirror symmetry structures withrespect to the second slit.

In one embodiment of the present disclosure, the first main electrode ofthe first sub-pixel electrode is substantially parallel to the firstslit, and the distance between the first main electrode and the firstslit is greater than that of the first main electrode of the firstsub-pixel electrode and the data line which is adjacent to the firstmain electrode of the first sub-pixel electrode, the first mainelectrode of the third sub-pixel electrode is substantially parallel tothe second slit, and the distance between the first main electrode ofthe third sub-pixel electrode and the second slit are greater than thatof the first main electrode of the third sub-pixel electrode and thedata line which is adjacent to the first main electrode of the thirdsub-pixel electrode.

In one embodiment of the present disclosure, the pixel array substratefurther includes a plurality of first switches and a plurality of secondswitches. The plurality of first switches respectively disposed on aside of each pixel area, a first end of each first switch iselectrically connected to respective first pixel electrode throughrespective first connecting line, a second end of each first switch iselectrically connected to corresponding data line and scan line. Theplurality of second switches respectively disposed on the side of eachpixel area and electrically connected to corresponding data line andscan line, each second switch is electrically connected to correspondingsecond pixel electrode through corresponding second connecting line.

In one embodiment of the present disclosure, each one of the pluralityof pixels further includes a charge-sharing capacitor and a thirdswitch. A first end of the charge-sharing capacitor is electricallyconnected to the first pixel electrode, a second end of thecharge-sharing capacitor is electrically connected to the second pixelelectrode through the third switch.

The present disclosure, in another aspect, relates to a pixel arraysubstrate includes a plurality of data lines, a plurality of scan lines,and a plurality of pixels. Each pixel includes a first pixel electrodewhich is electrically connected to corresponding data line and scanline, the first pixel electrode includes a first sub-pixel electrode anda second sub-pixel electrode. The second sub-pixel electrodeelectrically connected to the first sub-pixel electrode, wherein thefirst sub-pixel electrode and the second sub-pixel electrode are mirrorsymmetry structures with respect to a symmetry axis.

In one embodiment of the present disclosure, the symmetry axis issubstantially parallel to the plurality of data lines.

In one embodiment of the present disclosure, the distance between thesymmetry axis and one adjacent data line is the same as that between thesymmetry axis and the other adjacent data line.

In one embodiment of the present disclosure, the first sub-pixelelectrode includes a first main electrode, a second main electrode, aplurality of first branch electrodes, a plurality of second branchelectrodes, a plurality of third branch electrodes and a plurality offourth branch electrodes. The first main electrode and the second mainelectrode are electrically connected and are substantially orthogonallyarranged to define a first area, a second area, a third area and afourth area. The plurality of first branch electrodes is disposed in thefirst area. The plurality of second branch electrodes is disposed in thesecond area. The plurality of third branch electrodes is disposed in thethird area. The plurality of fourth branch electrodes is disposed in thefourth area, wherein the plurality of first branch electrodes, theplurality of second branch electrodes, the plurality of third branchelectrodes and the plurality of fourth branch electrodes areelectrically connected with one of the first main electrode and thesecond main electrode, the first branch electrodes are arranged parallelto each other, the second branch electrodes are arranged parallel toeach other, the third branch electrodes are arranged parallel to eachother and the fourth branch electrodes are arranged parallel to eachother, and the plurality of first branch electrodes, the plurality ofsecond branch electrodes, the plurality of third branch electrodes andthe plurality of fourth branch electrodes are respectively extend todifferent directions from the first main electrode or the second mainelectrode.

In one embodiment of the present disclosure, the first main electrode issubstantially parallel to the symmetry axis, and the distance betweenthe first main electrode and the symmetry axis is greater than thatbetween the first main electrode and the data line which is adjacent tothe first main electrode.

In one embodiment of the present disclosure, the pixel array substratefurther includes a second pixel electrode and a second connecting line.The second pixel electrode is electrically connected to correspondingdata line and scan line. The second pixel electrode is electricallyconnected to corresponding data line through the second connecting line,wherein the second connecting line is positioned along the direction ofthe symmetry axis.

In one embodiment of the present disclosure, the first pixel electrodeand the second pixel electrode are electrically connected to the samedata line.

In another embodiment of the present disclosure, the first pixelelectrode and the second pixel electrode are respectively electricallyconnected to different data lines.

In one embodiment of the present disclosure, the first pixel electrodehas a first slit which is along the direction of the symmetry axis toexpose a part of the second connecting line.

In one embodiment of the present disclosure, the pixel array substratefurther includes a third pixel electrode and a third sub-pixelelectrode. The third pixel electrode is disposed between the first pixelelectrode and the second pixel electrode, and electrically connected tocorresponding data line and scan line, the third pixel electrodeincludes a third sub-pixel electrode and a fourth sub-pixel electrode.The fourth sub-pixel electrode electrically connected to the thirdsub-pixel electrode, wherein the third sub-pixel electrode and thefourth sub-pixel electrode are mirror symmetry structures with respectto the symmetry axis.

In one embodiment of the present disclosure, the third sub-pixelelectrode and the fourth sub-pixel electrode respectively includes afirst main electrode, a second main electrode, a plurality of firstbranch electrodes, a plurality of second branch electrodes, a pluralityof third branch electrodes and a plurality of fourth branch electrodes.The first main electrode and the second main electrode are electricallyconnected and are substantially orthogonally arranged to define a firstarea, a second area, a third area and a fourth area. The plurality offirst branch electrodes is disposed in the first area. The plurality ofsecond branch electrodes is disposed in the second area. The pluralityof third branch electrodes is disposed in the third area. The pluralityof fourth branch electrodes is disposed in the fourth area, wherein theplurality of first branch electrodes, the plurality of second branchelectrodes, the plurality of third branch electrodes and the pluralityof fourth branch electrodes are electrically connected with one of thefirst main electrode and the second main electrode, the first branchelectrodes are arranged parallel to each other, the second branchelectrodes are arranged parallel to each other, the third branchelectrodes are arranged parallel to each other and the fourth branchelectrodes are arranged parallel to each other, and the plurality offirst branch electrodes, the plurality of second branch electrodes, theplurality of third branch electrodes and the plurality of fourth branchelectrodes respectively extend to different directions from the firstmain electrode or the second main electrode.

In one embodiment of the present disclosure, the first main electrode ofthe first sub-pixel electrode and the first main electrode of the thirdsub-pixel electrode are substantially parallel to the symmetry axis, andthe distance between the first main electrode and the symmetry axis isgreater then that between the first main electrode and adjacent dataline.

In one embodiment of the present disclosure, the first pixel electrodehas a first slit which is along the direction of the symmetry axis, andthe third pixel electrode has a second slit which is also along thedirection of the symmetry axis to expose a part of the second connectingline.

The present disclosure, in another aspect, relates to a LCD panel,includes the pixel array substrate aforementioned, an oppositesubstrate, and a liquid crystal layer. The opposite substrate isdisposed above the pixel array substrate. The liquid crystal layer isdisposed between the pixel array substrate and the opposite substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more fully understood by reading the followingdetailed description of the embodiment, with reference made to theaccompanying drawings as follows:

FIG. 1 illustrates a top-view of a part of the pixel layout of theconventional array substrate;

FIG. 2 illustrates the equivalent circuit diagram of the pixel layout ofthe array substrate illustrated in FIG. 1;

FIG. 3 illustrates a top-view of a part of one embodiment of the pixellayout of the pixel array substrate of the present disclosure;

FIG. 4 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 5 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 6 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 7(A) to FIG. 7(B) illustrate the simulation of the transmittance ofthe pixel array substrate of the present disclosure;

FIG. 8 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 9 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 10 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 11 illustrates a top-view of a part of another embodiment of thepixel layout of the pixel array substrate of the present disclosure;

FIG. 12 illustrates the equivalent circuit diagram of the pixel layoutof the pixel array substrate of the present disclosure illustrated inFIG. 11; and

FIG. 13 illustrates a schematic diagram of the LCD panel with the pixelarray substrate of the present disclosure.

DETAILED DESCRIPTION

The present disclosure is described by the following specificembodiments. Those with ordinary skill in the arts can readilyunderstand the other advantages and functions of the present inventionafter reading the disclosure of this specification. The presentdisclosure can also be implemented with different embodiments. Variousdetails described in this specification can be modified based ondifferent viewpoints and applications without departing from the scopeof the present disclosure.

As used herein, the singular forms “a,” “an” and “the” include pluralreferents unless the context clearly dictates otherwise. Therefore,reference to, for example, a data sequence includes aspects having twoor more such sequences, unless the context clearly indicates otherwise.

Reference will now be made in detail to the embodiments of the presentdisclosure, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

Referring FIG. 3, FIG. 3 illustrates a part of one embodiment of thepixel array substrate of the present disclosure. The pixel arraysubstrate of this embodiment includes data lines, scan lines and pixels.The scan lines are crossed to the data lines to define pixel areas. Thepixels are respectively disposed in the pixel areas. As illustrated inFIG. 3, two adjacent scan lines SL1, SL2 (the upper group of scan linesSL1, SL2 provides the scan signals to the pixel illustrated in FIG. 3,and the lower group of scan lines SL1, SL2 provides the scan signals tothe pixel which is not illustrated in FIG. 3) are crossed to twoadjacent data lines DL1, DL2. A pixel 300 is disposed in a pixel areawhich is defined by two adjacent scan lines SL1 and two adjacent datalines DL1, DL2. The pixel 300 includes a first pixel electrode 302, afirst connecting line 306, a second pixel electrode 304 and a secondconnecting line 308. The first pixel electrode 302 is electricallyconnected to data line DL1 through the first connecting line 306, andthe second pixel electrode 304 is electrically connected to data lineDL1 through the second connecting line 308. The area of the first pixelelectrode 302 and the second pixel electrode 304 may be different. Inthe present embodiment and the following embodiments illustrated in FIG.4 and FIG. 5, the area of the second pixel electrode 304 is greater thanthat of the first pixel electrode 302, however, the present disclosureis not limited thereto. For example, the pattern of the first pixelelectrode 302 and the second pixel electrode 304 are both fishbonepatterns. In the present embodiment, the first pixel electrode 302 andthe second pixel electrode 304 are simultaneously charged by inputting ascan signal via scan line SL1 to turn on the first switch 310 and thesecond switch 312 in the same time sequence, and the first pixelelectrode 302 and the second pixel electrode 304 are simultaneouslycharged in the voltage of data line DL1. In next time sequence, thefirst pixel electrode 302 and the second pixel electrode 304 performcharge sharing, thus the voltage of the first pixel electrode 302 isdifferent from that of the second pixel electrode 304. For example, theway of charge sharing may be that pixel 300 further includes a thirdswitch T3 and charge-sharing capacitor Cs. One end of the charge-sharingcapacitor Cs is electrically connected to the first pixel electrode 302,and the other end of the charge-sharing capacitor Cs is electricallyconnected to the second pixel electrode 304 through the third switch T3.The third switch T3 is turned on by a signal passing through scan lineSL2, and the electric charges flow from the second pixel electrode 304to the capacitor C_(CSA) and C_(CSB). Therefore the voltage of the firstpixel electrode 302 is increased and the voltage of the second pixelelectrode 304 is decreased. However, the present disclosure is notlimited thereto. It should be noticed that, the first pixel electrode302 has a first slit 314, and the second connecting line 308 of thesecond pixel electrode 304, which electrically connects the second pixelelectrode 304 and its corresponding data line DL1 and scan line SL1, isexposed by the first slit 314. Therefore, the overlapping structure ofthe second connecting line 308 and the first pixel electrode 202 invertical direction is much less than that of the conventional structure.Accordingly, the coupling capacitance Cx induced by the overlappingstructure is minimized. As illustrated in FIG. 3 and FIG. 4, the firstslit 314 can be an open slit, but not limited to it. As illustrated inFIG. 5, the first slit 314 can be a closed slit, but not limited to iteither. When charge sharing is performed to decrease the voltage of thesecond pixel electrode 304 and increase the voltage of the first pixelelectrode 302 through the charge-sharing capacitor, the difficulty ofincreasing the voltage difference between the first pixel electrode andthe second pixel electrode is improved. Since the coupling capacitanceCx in the present embodiment is much less than that of conventionalarts, increasing the voltage difference between the first pixelelectrode and the second pixel electrode is much easier. Accordingly, itis not necessary to further increase the capacitance of thecharge-sharing capacitor Cs to decrease the voltage of the second pixelelectrode 304. Therefore, the voltage of the first pixel electrode 302of the present embodiment is higher than that of conventional arts, thevoltage of the second pixel electrode 304 of the present embodiment isalso higher than that of conventional arts, and the voltage difference(between the first pixel electrode 302 and the second pixel electrode304) of the present embodiment is substantially equal to that ofconventional arts. Accordingly, the present embodiment of the presentdisclosure is not only capable to improve the issue of color washout,but also enhance the LC efficiency of the LCD panel.

Referring to FIG. 6, FIG. 6 is a part of another embodiment of the pixelarray substrate of the present disclosure. The pixel array substrate ofthis embodiment includes data lines, scan lines and pixels. The scanlines are crossed to the data lines to define pixel areas. The pixelsare respectively disposed in the pixel areas. That is, each pixel isrespectively disposed in each pixel area. As illustrated in FIG. 6, twoadjacent scan lines SL1, SL2 (the upper group of scan line SL1, SL2provides the scan signals to the pixel illustrated in FIG. 6, and thelower group of scan line SL1, SL2 provides the scan signals to the pixelwhich is not illustrated) are crossed to two adjacent data line DL1,DL2. A pixel 600 is disposed in a pixel area which is defined by twoadjacent scan lines SL1 and two adjacent data lines DL1, DL2. The pixel600 includes a first pixel electrode 602, a first connecting line 306, asecond pixel electrode 304, and a second connecting line 308. The areaof the first pixel electrode 302 and the second pixel electrode 304 maybe different. In the present embodiment, the area of the second pixelelectrode 304 is greater than that of the first pixel electrode 602,however, the present disclosure is not limited thereto. The pattern ofthe second pixel electrode 304, for example, is the same as theaforementioned second pixel electrode 304 illustrated in FIGS. 3-5. Thefirst pixel electrode 602 is electrically connected to data line DL1 andscan line SL1 through the first connecting line 306 and the first switch310 respectively. The second pixel electrode 304 is electricallyconnected to data line DL1 and scan line SL1 through the secondconnecting line 308 and the second switch 312 respectively. The firstpixel electrode 602 has the first slit 314, and the second connectingline 308 of the second pixel electrode 304, which electrically connectsthe second pixel electrode 304 and its corresponding data line DL1 andscan line SL1, is exposed by the first slit 314. It should be noticedthat the first pixel electrode 602 includes the first sub-pixelelectrode 602 a and the second sub-pixel electrode 602 b. The first slit314 is between the first sub-pixel electrode 602 a and the secondsub-pixel electrode 602 b. The first sub-pixel electrode 602 a and thesecond sub-pixel electrode 602 b are mirror symmetry structures withrespect to the first slit 314. As illustrated in FIG. 6, the firstsub-pixel electrode 602 a includes a first main electrode 602 aT1, asecond main electrode 602 aT2, first branch electrodes 602 aS1, secondbranch electrodes 602 aS2, third branch electrodes 602 aS3 and fourthbranch electrodes 602 aS4. The first main electrode 602 aT1 and thesecond main electrode 602 aT2 are electrically connected and aresubstantially orthogonally arranged to define a first area, a secondarea, a third area and a fourth area. The first branch electrodes 602aS1, second branch electrodes 602 aS2, third branch electrodes 602 aS3and fourth branch electrodes 602 aS4 are respectively disposed in thefirst area, the second area, the third area and the fourth area. Thefirst branch electrodes 602 aS1, second branch electrodes 602 aS2, thirdbranch electrodes 602 aS3 and fourth branch electrodes 602 aS4 areelectrically connected with one of the first main electrode 602 aT1 andthe second main electrode 602 aT2. The first branch electrodes 602 aS1are arranged parallel to each other, the second branch electrodes 602aS2 are arranged parallel to each other, the third branch electrodes 602aS3 are arranged parallel to each other and the fourth branch electrodes602 aS4 are arranged parallel to each other. The first branch electrodes602 aS1, the second branch electrodes 602 aS2, the third branchelectrodes 602 aS3 and the fourth branch electrodes 602 aS4 arerespectively extend to different directions from the first mainelectrode 602 aT1 or the second main electrode 602 aT2. To be morespecific, each first branch electrode 602 aS1 is electrically connectedto the first main electrode 602 aT1 or the second main electrode 602aT2, and each first branch electrode 602 aS1 are arranged in paralleland extends outward along the direction S1. And so on the second branchelectrodes 602 aS2, the third branch electrodes 602 aS3, and the fourthbranch electrodes 602 aS4 are also arranged similarly to the firstbranch electrodes 602 aS1. The difference among them is only theirrespective extending directions. In other word, each second branchelectrode 602 aS2 are arranged in parallel and extends outward along thedirection S2; each third branch electrode 602 aS3 are arranged inparallel and extends outward along the direction S3; and each fourthbranch electrode 602 aS4 are arranged in parallel and extends outwardalong the direction S4.

In comparison with the pattern of the first pixel electrode 602illustrated in FIG. 6 to that of the first pixel electrode 302illustrated in FIG. 3, the first pixel electrode 602 illustrated in FIG.6 has more main electrodes (such as the first main electrode 602 aT1 andthe second main electrode 602 aT2) than that of the first pixelelectrode 302 illustrated in FIG. 3. Accordingly, stronger electricfield is provided to each branch electrode (such as the first branchelectrodes 602 aS1, the second branch electrodes 602 aS2, the thirdbranch electrodes 602 aS3, and the fourth branch electrodes 602 aS4 ofthe first sub-pixel electrode 602 a), thus better control of the tiltingangle of the LC molecules which are corresponding to the first pixelelectrode 602 is also provided than that of the first pixel electrode302 illustrated in FIG. 3.

Referring to FIG. 7, the main electrodes offer stronger electric fieldthan the branch electrodes do. However, the electric field offered bythe main electrodes does not possess specific direction as that offeredby the branch electrodes. Therefore, the LC molecules corresponding tothe main electrodes do not tilt in one specific direction, and thetransmittance corresponding to the main electrodes is substantiallyzero. Accordingly, the positions, which are corresponded to the mainelectrodes of the LCD panel, usually display black lines.

FIG. 7(A) illustrates the transmittance simulation of the first pixelelectrode 302 (as aforementioned embodiments in FIGS. 3-5). The slit 314can be regarded as the edge of the domain of the pixel electrode 302.The electric field at the edge of the domain of the pixel electrode 302will conflict with that in adjacent data line. Therefore, thecontrolling of the electric field of the whole pixel electrode is weak.Accordingly, the black lines in vertical direction could randomly appearin any region of the whole pixel electrode. In contrast, FIG. 7(B)illustrates the transmittance simulation of the first pixel electrodehaving the main electrodes (as the first sub-pixel electrode 602 a andthe second sub-pixel electrode 602 b in FIG. 6). Because the mainelectrodes in vertical direction improve the control of the electricfield of the whole pixel electrode, the LC molecules will tilt along theslits which are between the branches of the sub-pixel electrode. Theissue of LC molecules tilting conflicts does not occur, hence the blacklines in vertical direction can be restricted in the positions along avertical direction which are corresponded to the main electrodes.Therefore, the first sub-pixel electrode 602 a and the second sub-pixelelectrode 602 b (illustrated in FIG. 6) control the positions of theblack lines better than the pixel electrode 302 (illustrated in FIG. 3)do.

Referring to FIG. 6 again, the first main electrode 602 aT1 issubstantially parallel to the first slit 314, and the distance betweenthe first main electrode 602 aT1 and the first slit 314 is greater thanthat between the first main electrode 602 aT1 and the data line DL1which is adjacent to the first main electrode 602 aT1. The first mainelectrode 602 aT1 is substantially between data line DL1 and the firstslit 314. That is, the first main electrode 602 aT1 is disposed at theedge of the pixel area. Therefore, the black lines in vertical directioncan be restricted at the edge of the pixel area by the main electrodesin vertical direction. Accordingly, the open ratio of the pixel isincreased. In summary, the embodiment illustrated in FIG. 6 of thepresent disclosure not only minimizes the issue caused by the couplingcapacitor Cx and improves the LC efficiency of the LCD panel, but alsoimproves the open ratio of the pixel by restricting the black lines atthe edge of the pixel are.

Referring to FIG. 8, FIG. 8 illustrates a part of the pixel arraysubstrate of another embodiment of the present disclosure. Theconnections between each element are similar to described above,therefore the details are omitted here. It should be noticed that thefirst connecting line 306 and the second connecting line 308 arerespectively electrically connected to different data lines. The firstconnecting line 306 is electrically connected to data line DL1 throughthe first switch 310, the second connecting line 308 is electricallyconnected to data line DL2 through the second switch 312. Therefore, thefirst pixel electrode 602 and the second pixel electrode 304 can berespectively charged with different voltages by data line DL1 and dateline DL2 in the same time sequence. Specifically, in one time sequence,one scan signal is transmitted by the same scan line SL1 and the firstswitch 310 and the second switch 312 are turned on, so that the firstpixel electrode 602 and the second pixel electrode 304 can be chargedwith data line DL1 and data line DL2 respectively and possessesdifferent voltages.

Referring FIG. 9, FIG. 9 illustrates a part of the pixel array substrateof another embodiment of the present disclosure. The pixel arraysubstrate of this embodiment includes data lines, scan lines and pixels.The scan lines are crossed to the data lines to define pixel areas. Thepixels are respectively disposed in the pixel areas. Each pixel isrespectively disposed in each pixel area. As illustrated in FIG. 9, twoadjacent scan lines SL1, SL2 (the upper group of scan line SL1, SL2provides the scan signals to the pixel illustrated in FIG. 9, and thelower group of scan line SL1, SL2 provides the scan signals to the pixelwhich is not illustrated in FIG. 9) are crossed to two adjacent datalines DL1, DL2. A pixel 900 is disposed in the pixel area which isdefined by two adjacent scan lines SL1 and two adjacent data lines DL1,DL2. The pixel 900 includes a first pixel electrode 902, a firstconnecting line 306, a second pixel electrode 304 and a secondconnecting line 308. The first pixel electrode 902 is electricallyconnected to data line DL1 and scan line SL1 through the firstconnecting line 306 and the first switch 310 respectively, and thesecond pixel electrode 304 is electrically connected to data line DL1and scan line SL1 through the second connecting line 308 and the secondswitch 312 respectively. It should be noticed that, the first pixelelectrode 902 includes a first sub-pixel electrode 902 a and a secondsub-pixel electrode 902 b. The first sub-pixel electrode 902 a and thesecond sub-pixel electrode 902 b are mirror symmetry structures withrespect to a symmetry axis 914. Two adjacent data lines DL1, DL2 arealso mirror symmetry structures with respect to the symmetry axis 914.The distance between the symmetry axis 914 and the data line DL1 may besubstantially the same as the distance between the symmetry axis 914 andthe data line DL2. In addition, the first pixel electrode 902 mayinclude the first sub-pixel electrode 902 a and the second sub-pixelelectrode 902 b (the same as that illustrated in FIG. 6), and thepattern of the first sub-pixel electrode 902 a and the second sub-pixelelectrode 902 b also can be the same as that illustrated in FIG. 6.Therefore, the details are omitted here. However, it should be noticedthat, the first pixel electrode 902 illustrated in FIG. 9 does not havethe first slit 314 as the first pixel electrode 602 illustrated in FIG.6. More specifically, the first sub-pixel electrode 902 a and the secondsub-pixel electrode 902 b of the first pixel electrode 902 are notseparated as the first sub-pixel electrode 602 a and the secondsub-pixel electrode 602 b of the first pixel electrode 602 are separatedby the first slit 314. In contrast, the first sub-pixel electrode 902 aand the second sub-pixel electrode 902 b are connected by some of theirbranch electrodes. There are slits between those connected branchelectrodes to expose part of the second connecting line 308. As shown inFIG. 9, the first main electrode of the present embodiment can also bedisposed at the edge of the pixel area to increase the open ratio of thepixel. Besides, the overlapping of the second connecting line 308 andthe first pixel electrode 902 in vertical direction is also less thanthat of conventional arts (as shown in FIG. 1). It results in that thecoupling capacitance Cx generated by the overlapping of the secondconnecting line 308 and the first pixel electrode 902 is reduced.Accordingly, the pixel array substrate of the present embodiment doesnot only improve the open ratio within each pixel on the pixel arraysubstrate, but also reduce the issue which is caused by the couplingcapacitance Cx in conventional arts. Therefore, the target of solvingcolor washout is achieved, and the LC efficiency of the LCD panel isalso improved.

Referring to FIG. 10, FIG. 10 illustrates a part of the pixel arraysubstrate of another embodiment of the present disclosure. Theconnections of elements are similar to those described in lastparagraph; therefore the details are omitted here. The only differencein the present embodiment is that the first connecting line 306 and thesecond connecting line 308 are electrically connected to different datalines. Specifically, the first connecting line 306 is electricallyconnected to data line DL1 through the first switch 310, and the secondconnecting line 308 is electrically connected to data line DL2 throughthe second switch 312. Therefore, the first pixel electrode 902 and thesecond pixel electrode 304 can be respectively charged with differentvoltages by data line DL1 and date line DL2 in the same time sequence.Specifically, in one time sequence, one scan signal is transmitted bythe same scan line SL1 and the first switch 310 and the second switch312 are turned on, so that the first pixel electrode 902 and the secondpixel electrode 304 can be charged with data line DL1 and data line DL2respectively and possesses different voltages.

Referring to FIG. 11, FIG. 11 illustrates a part of the pixel arraysubstrate of another embodiment of the present disclosure. The elementsin FIG. 11 which are the same as those in FIG. 6 are labeled the same.The connections between those elements are also the same asaforementioned, and the details are omitted here. It should be noticedthat the pixel in FIG. 11 further includes a third pixel electrode 1102,a fourth switch 1110 and a third connecting line 1118. The third pixelelectrode 1102 is electrically connected to corresponding data line DL1through the third connecting line 1118 and the fourth switch 1110, andthe third pixel electrode 1102 has a second slit 1114. The third pixelelectrode 1102 can be disposed between the first pixel electrode 602 andthe second pixel electrode 304. However, the present disclosure is notlimited thereto. The third connecting line 1118 may be disposed at theedge of the first pixel electrode 602 or the second pixel electrode 304,but the present disclosure is still not limited thereto. As long as thethird connecting line 1118 is not overlapped with the first pixelelectrode 602 and the second pixel electrode 304 in vertical direction,the coupling capacitance Cx is not induced. Besides, as illustrated inFIG. 12 (FIG. 12 illustrates the equivalent circuit diagram of FIG. 11),the first switch 310 is electrically connected between data line DL1 andthe first pixel electrode 602. The first switch 310 is also electricallyconnected to scan line SL1, and is controlled by the input signals fromscan line SL1. The storage capacitor C_(ST1) is electrically connectedbetween the first pixel electrode 602 and the common electrode V_(COM).When the first switch 310 is turned on, the data signal of data line DL1is transmitted to the storage capacitor C_(ST1) and the first pixelelectrode 602 through the first switch 310. The storage capacitorC_(ST1) and the first pixel electrode 602 are charged to correspondingvoltages according to the data signals. The second switch 312 iselectrically connected between data line DL1 and the second pixelelectrode 304. The second switch 312 is also electrically connected toscan line SL1, and is controlled by the input signals from scan lineSL1. The storage capacitor C_(ST2) is electrically connected between thesecond pixel electrode 304 and the common electrode V_(COM). When thesecond switch 312 is turned on, the data signal of data line DL1 istransmitted to the storage capacitor C_(ST2) through the second switch310, so that the storage capacitor C_(ST2) is charged to correspondingvoltage according to the data signal. The fourth switch 1110 iselectrically connected between data line DL1 and the third pixelelectrode 1102. The fourth switch 1110 is also electrically connected toscan line SL1, and is controlled by the input signals from scan lineSL1. The storage capacitor C_(ST3) is electrically connected between thethird pixel electrode 1102 and the common electrode V_(COM). When thefourth switch 1110 is turned on, the data signal of data line DL1 istransmitted to the storage capacitor C_(ST3) through the fourth switch1110, so that the storage capacitor C_(ST3) is charged to correspondingvoltage according to the data signal. Accordingly, the liquid crystalcapacitors C_(LC 1-3) and the storage capacitors C_(ST1-3) are chargedto their corresponding voltages in the same time. Further, to solve theissue of color washout of LCD panels, charge sharing is performed. Thatis, in next time sequence right after the signal is transmitted by scanline SL1, the first switch 316 is turned on by the signal which istransmitted by scan line SL2. One part of the voltage of the secondpixel electrode 304 is shared to the capacitor C_(CSB) and the otherpart of the voltage of the second pixel electrode 304 is shared to thecapacitor C_(CSA). In other words, charge sharing is performed betweenthe first pixel electrode 602 and the second pixel electrode 304 throughthe charge-sharing capacitor Cs so that the voltage of the first pixelelectrode 602 increases and the voltage of the second pixel electrode304 decreases. In the other hand, the third pixel electrode 1102 is notrelevant to the charge sharing but keeps its original voltage. As aresult, the first pixel electrode 602, the second pixel electrode 304and the third pixel electrode 1102 possesses different voltages, and theLC molecules of different pixel areas (which are corresponded to thefirst pixel electrode 602, the second pixel electrode 304, and the thirdpixel electrode 1102 respectively) have different tilting angles.Accordingly, different transmittances within one pixel are achieved, soas the issue of color washout can be improved.

Referring to FIG. 11, the third pixel electrode 1102 includes a thirdsub-pixel electrode 1102 a and a fourth sub-pixel electrode 1102 b. Thesecond slit 1114 is substantially disposed between the third sub-pixelelectrode 1102 a and the fourth sub-pixel electrode 1102 b, and thesecond slit 1114 is substantially positioned along the extending line ofthe first slit 314. The third sub-pixel electrode 1102 a and the fourthsub-pixel electrode 1102 b of the third pixel electrode 1102 are similarto the first sub-pixel electrode 602 a and the second sub-pixelelectrode 602 b of the first pixel electrode. The third sub-pixelelectrode 1102 a and the fourth sub-pixel electrode 1102 b are mirrorsymmetry structures with respect to the second slit 1114, and thepattern of the third sub-pixel electrode 1102 a may be the same as thatof the first sub-pixel electrode 602 a, but not limited to it. It shouldbe noticed that, in the present embodiment, the second connecting line308 is exposed by both the first slit 314 of the first pixel electrode602 and the second slit 1114 of the third pixel electrode 1102.Accordingly, the coupling capacitance Cx in the present embodiment ismuch less than that of conventional arts, the difficulty of increasingthe voltage difference between the first pixel electrode and the secondpixel electrode is improved. Since the coupling capacitance Cx in thepresent embodiment is much less than that of conventional arts,increasing the voltage difference between the first pixel electrode andthe second pixel electrode is much easier. Accordingly, it is notnecessary to further increase the capacitance of the charge-sharingcapacitor Cs. The present embodiment of the present disclosure is notonly capable to improve the issue of color washout, but also enhance theLC efficiency of the LCD panel to approximately 12.45%. Asaforementioned, the locations of the black lines can be also controlledand restricted at the edge of the pixel area by special pattern designof pixel electrodes (602 a, 602 b, 1102 a, and 1102 b). Therefore, theopen ratio of the pixel can be further increased. In another embodimentof the present disclosure, the structures of the first sub-pixelelectrode 602 a, the second sub-pixel electrode 602 b, the thirdsub-pixel electrode 1102 a and the fourth sub-pixel electrode 1102 b canbe designed as the structures of the first sub-pixel electrode 902 a andthe second sub-pixel electrode 902 b. That is, the first sub-pixelelectrode 602 a and the third sub-pixel electrode 1102 a are designed asthe first sub-pixel electrode 902 a, and the second sub-pixel electrode602 b and the fourth sub-pixel electrode 1102 b are designed as thesecond sub-pixel electrode 902 b so that the first sub-pixel electrode602 a and the second sub-pixel electrode 602 b are mirror symmetrystructures with respect to the symmetry axis 914, and the thirdsub-pixel electrode 1102 a and the fourth sub-pixel electrode 1102 b arealso mirror symmetry structures with respect to the symmetry axis 914.Accordingly, the LC efficiency and the open ratio of the pixel arraysubstrate of the present embodiment are also improved under the premiseof solving the issue of color washout.

Referring to FIG. 13, FIG. 13 illustrates the LCD panel 1300 of thepresent disclosure. The LCD panel 1300 includes a pixel array substrate1302, an opposite substrate 1304 and a liquid crystal layer 1306. Thepixel array substrate 1302 can be any one of aforementioned embodimentsof pixel array substrate of the present disclosure. The oppositesubstrate 1304 is disposed on the pixel array substrate 1302, and theliquid crystal layer 1306 is disposed between the pixel array substrate1302 and the opposite substrate 1304. According to the structure of LCDpanel 1300, different opposite substrate 1304 can be correspondinglychosen to cope with the LCD panel 1300. The material of the liquidcrystal layer 1306 can be chosen the liquid crystals with an adequatedielectric anisotropy (Δ∈), and a birefringence (Δn). The birefringence(Δn) of the liquid crystals can also be coped with an adequate cell gapof the liquid crystal layer 1306 to achieve the predeterminedtransmittance. The opposite substrate 1304 can optionally furtherincludes a color filter. The opposite substrate 1304 can also be calleda color filter substrate.

It should be noticed that the pixel array substrate of the presentdisclosure has a whole new design of pixel layout. Therefore, thecoupling capacitance Cx of the pixel array substrate in the presentdisclosure is much less than that of prior arts, the difficulty ofincreasing the voltage difference between the first pixel electrode andthe second pixel electrode is obviously improved. Accordingly, LCefficiency and the open ratio of the pixel array substrate of thepresent disclosure are also improved under the premise of solving theissue of color washout.

Although the present disclosure has been described in considerabledetail with reference to certain embodiments thereof, other embodimentsare possible. Therefore, the spirit and scope of the appended claimsshould not be limited to the description of the embodiments containedherein.

It will be apparent to those ordinarily skilled in the art that variousmodifications and variations may be made to the structure of the presentdisclosure without departing from the scope or spirit of the disclosure.In view of the foregoing, it is intended that the present disclosurecover modifications and variations thereof provided they fall within thescope of the following claims.

What is claimed is:
 1. A pixel array substrate, comprising: a pluralityof pixels comprising: a first pixel electrode having a first slit; afirst connecting line electrically connected to the first pixelelectrode; a second pixel electrode; and a second connecting line,electrically connected to the second pixel electrode, wherein at least apart of the second connecting line is exposed by the first slit of thefirst pixel electrode, the first pixel electrode comprises a firstsub-pixel electrode and a second sub-pixel electrode, the first slit issubstantially positioned between the first sub-pixel electrode and thesecond sub-pixel electrode, and the first sub-pixel electrode comprises:a first main electrode; a second main electrode, the first mainelectrode and the second main electrode being electrically connected andare substantially orthogonally arranged to define a first area, a secondarea, a third area and a fourth area; a plurality of first branchelectrodes disposed in the first area; a plurality of second branchelectrodes disposed in the second area; a plurality of third branchelectrodes disposed in the third area; and a plurality of fourth branchelectrodes disposed in the fourth area, wherein the plurality of firstbranch electrodes, the plurality of second branch electrodes, theplurality of third branch electrodes and the plurality of fourth branchelectrodes are electrically connected with at least one of the firstmain electrode and the second main electrode, the first branchelectrodes are arranged parallel to each other, the second branchelectrodes are arranged parallel to each other, the third branchelectrodes are arranged parallel to each other and the fourth branchelectrodes are arranged parallel to each other, and the plurality offirst branch electrodes, the plurality of second branch electrodes, theplurality of third branch electrodes and the plurality of fourth branchelectrodes respectively extend to different directions from the firstmain electrode or the second main electrode.
 2. The pixel arraysubstrate of claim 1, wherein the first slit is an open slit.
 3. Thepixel array substrate of claim 1, wherein the first slit is a closedslit.
 4. The pixel array substrate of claim 1, further comprising: aplurality of data lines; a plurality of scan lines crossed to theplurality of data lines to define a plurality of pixel areas, whereinthe pixels are respectively disposed in the plurality of pixel areas,and the first connecting line and the second connecting line areelectrically connected to a data line of the plurality of data lines. 5.The pixel array substrate of claim 4, wherein the first main electrodeis substantially parallel to the first slit, and the distance betweenthe first main electrode and the first slit is greater than that betweenthe first main electrode and the data line of the plurality of datalines.
 6. The pixel array substrate of claim 1, further comprising: aplurality of data lines; a plurality of scan lines crossed to theplurality of data lines to define a plurality of pixel areas, whereinthe pixels are respectively disposed in the plurality of pixel areas,and the first connecting line and the second connecting line areelectrically connected to different data lines of the plurality of datalines.
 7. The pixel array substrate of claim 1, wherein the firstsub-pixel electrode and the second sub-pixel electrode are mirrorsymmetry structures with respect to the first slit.
 8. The pixel arraysubstrate of claim 1, wherein each of the pixels further comprises: athird pixel electrode having a second slit; and a third connecting lineelectrically connected to the third pixel electrode; wherein at least apart of the second connecting line is exposed by the first slit of thefirst pixel electrode and the second slit of the third pixel electrode.9. The pixel array substrate of claim 8, further comprising: a pluralityof data lines; a plurality of scan lines crossed to the plurality ofdata lines to define a plurality of pixel areas, wherein the pixels arerespectively disposed in the plurality of pixel areas, and the firstconnecting line and the third connecting line are electrically connectedto a data line of the plurality of data lines.
 10. The pixel arraysubstrate of claim 8, wherein the third connecting line is disposed onan edge of the first sub-pixel electrode, the third pixel electrodecomprises a third sub-pixel electrode and a fourth sub-pixel electrode,the second slit is substantially positioned between the third sub-pixelelectrode and the fourth sub-pixel electrode, and the second slit issubstantially positioned along the extending line of the first slit, thefirst sub-pixel electrode and the second sub-pixel electrode are mirrorsymmetry structures with respect to the first slit, the third sub-pixelelectrode and the fourth sub-pixel electrode are mirror symmetrystructures with respect to the second slit.
 11. The pixel arraysubstrate of claim 10, wherein the third sub-pixel electrode and thefourth sub-pixel electrode respectively comprise: a first mainelectrode; a second main electrode, the first main electrode and thesecond main electrode being electrically connected and are substantiallyorthogonally arranged to define a first area, a second area, a thirdarea and a fourth area; a plurality of first branch electrodes disposedin the first area; a plurality of second branch electrodes disposed inthe second area; a plurality of third branch electrodes disposed in thethird area; and a plurality of fourth branch electrodes disposed in thefourth area, wherein the plurality of first branch electrodes, theplurality of second branch electrodes, the plurality of third branchelectrodes and the plurality of fourth branch electrodes areelectrically connected with one of the first main electrodes and thesecond main electrodes, the first branch electrodes are arrangedparallel to each other, the second branch electrodes are arrangedparallel to each other, the third branch electrodes are arrangedparallel to each other and the fourth branch electrodes are arrangedparallel to each other, and the plurality of first branch electrodes,the plurality of second branch electrodes, the plurality of third branchelectrodes and the plurality of fourth branch electrodes respectivelyextend to different directions from the first main electrode or thesecond main electrode, the first sub-pixel electrode and the secondsub-pixel electrode are mirror symmetry structures with respect to thefirst slit, the third sub-pixel electrode and the fourth sub-pixelelectrode are mirror symmetry structures with respect to the secondslit, the first main electrode of the first sub-pixel electrode issubstantially parallel to the first slit, the first main electrode ofthe third sub-pixel electrode is substantially parallel to the secondslit.
 12. The pixel array substrate of claim 1, further comprising: aplurality of first switches respectively disposed on a side of each ofthe pixel areas, a first end of each first switch being electricallyconnected to the respective first pixel electrodes through the firstconnecting line; and a plurality of second switches respectivelydisposed on the side of each of the pixel areas, each of the secondswitches being electrically connected to the second pixel electrodethrough the second connecting line.
 13. The pixel array substrate ofclaim 12, wherein each one of the plurality of pixels further comprises:a charge-sharing capacitor; and a third switch, wherein a first end ofthe charge-sharing capacitor is electrically connected to the firstpixel electrode, and a second end of the charge-sharing capacitor iselectrically connected to the second pixel electrode through the thirdswitch.
 14. A pixel array substrate, comprising: a plurality of datalines; a plurality of scan lines crossed to the plurality of data linesto define a plurality of pixel areas; and a plurality of pixelsrespectively disposed in the plurality of pixel areas, each of thepixels comprising: a first pixel electrode electrically connected to oneof the plurality of data lines and one of the plurality of scan lines,the first pixel electrode having a first slit; a first connecting line,the first pixel electrode electrically connected to a data line of theplurality of data lines through the first connecting line; a secondpixel electrode electrically connected to the data line or another oneof the plurality of data lines and the scan line of the plurality ofscan lines, wherein the second pixel electrode comprises a first mainelectrode paralleled to the data line of the plurality of data lines;and a second connecting line, the second pixel electrode electricallyconnected to the data line or the another one of the plurality of datalines through the second connecting line, wherein at least a part of thesecond connecting line is exposed by the first slit of the first pixelelectrode, and the second connecting line is connected to the first mainelectrode of the second pixel electrode.
 15. The pixel array substrateof claim 14, wherein the first slit is substantially parallel to thedata line of the plurality of data lines.
 16. The pixel array substrateof claim 14, wherein the second pixel electrode further comprises: asecond main electrode, the first main electrode and the second mainelectrode being electrically connected and are substantiallyorthogonally arranged to define a first area, a second area, a thirdarea and a fourth area; a plurality of first branch electrodes disposedin the first area; a plurality of second branch electrodes disposed inthe second area; a plurality of third branch electrodes disposed in thethird area; and a plurality of fourth branch electrodes disposed in thefourth area, wherein the plurality of first branch electrodes, theplurality of second branch electrodes, the plurality of third branchelectrodes and the plurality of fourth branch electrodes areelectrically connected with at least one of the first main electrode andthe second main electrode, the first branch electrodes are arrangedparallel to each other, the second branch electrodes are arrangedparallel to each other, the third branch electrodes are arrangedparallel to each other and the fourth branch electrodes are arrangedparallel to each other, and the plurality of first branch electrodes,the plurality of second branch electrodes, the plurality of third branchelectrodes and the plurality of fourth branch electrodes respectivelyextend to different directions from the first main electrode or thesecond main electrode.
 17. The pixel array substrate of claim 14,wherein the first pixel electrode comprises a first sub-pixel electrodeand a second sub-pixel electrode, the first slit is substantiallypositioned between the first sub-pixel electrode and the secondsub-pixel electrode, and the first sub-pixel electrode comprises: afirst main electrode; a second main electrode, the first main electrodeand the second main electrode being electrically connected and aresubstantially orthogonally arranged to define a first area, a secondarea, a third area and a fourth area; a plurality of first branchelectrodes disposed in the first area; a plurality of second branchelectrodes disposed in the second area; a plurality of third branchelectrodes disposed in the third area; and a plurality of fourth branchelectrodes disposed in the fourth area, wherein the plurality of firstbranch electrodes, the plurality of second branch electrodes, theplurality of third branch electrodes and the plurality of fourth branchelectrodes are electrically connected with at least one of the firstmain electrode and the second main electrode of the first sub-pixelelectrode, and the plurality of first branch electrodes, the pluralityof second branch electrodes, the plurality of third branch electrodesand the plurality of fourth branch electrodes respectively extend todifferent directions from the first main electrode or the second mainelectrode.
 18. The pixel array substrate of claim 17, wherein the firstmain electrode of the first sub-pixel electrode is substantiallyparallel to the first slit, and the distance between the first mainelectrode of the first sub-pixel electrode and the first slit is greaterthan that between the first main electrode of the first sub-pixelelectrode and the data line of the plurality of data lines.
 19. Thepixel array substrate of claim 14, wherein each of the pixels furthercomprises: a third pixel electrode electrically connected to the dataline of the plurality of data lines and the scan line of the pluralityof scan lines, the third pixel electrode having a second slit; and athird connecting line, the third pixel electrode electrically connectedto the data line of the plurality of data lines through the thirdconnecting line; wherein at least a part of the second connecting lineis exposed by the first slit of the first pixel electrode and the secondslit of the third pixel electrode.
 20. The pixel array substrate ofclaim 19, wherein the third connecting line is disposed on an edge ofthe first sub-pixel electrode, the third pixel electrode comprises athird sub-pixel electrode and a fourth sub-pixel electrode, the secondslit is substantially positioned between the third sub-pixel electrodeand the fourth sub-pixel electrode, and the second slit is substantiallypositioned along the extending line of the first slit, the first slitand the second slit are substantially parallel to the plurality of datalines, the first sub-pixel electrode and the second sub-pixel electrodeare mirror symmetry structures with respect to the first slit, and thethird sub-pixel electrode and the fourth sub-pixel electrode are mirrorsymmetry structures with respect to the second slit.